With the advent of new digital technologies, consumer products, such as battery operated selective call receivers, are utilizing high-speed analog-to-digital converters (ADC's) to replace a substantial portion of conventional radio demodulation circuits. This change in design is driven by advancements in the development of ADC's. One such advancement is the sigma-delta converter. Particularly, sigma-delta converters have been used because of their simplicity and their advantageous noise characteristics over other conventional ADC's such as successive approximation ADC's. A characteristic of sigma-delta converters, which makes them unique from other converters, is the technique of oversampling the input signal (by, e.g., five-times the Nyquist frequency). This oversampling technique, however, becomes disadvantageous when the input signal is not at a low frequency, e.g., baseband.
FIG. 1 shows an electrical block diagram of a prior art bandpass sigma-delta converter 100. The bandpass sigma-delta converter 100 comprises a difference circuit 104, a bandpass filter 108, a sigma-delta converter 114, and a digital-to-analog converter (DAC) 118. During normal operation, the difference circuit 104 combines an analog input signal 102 with an analog feedback signal 120 to produce an analog output signal 106. In this example, the analog input signal 102 operates at a given intermediate or carrier frequency (e.g., 200 MHz). The analog output signal 106 is then filtered by the bandpass filter 108 at the center frequency of the signal to produced a filtered analog signal 110. The filtered analog signal 110 is then converted by the sigma-delta converter 114 to a digital signal 116. Finally, the digital signal 116 is converted to the analog feedback signal 120 by the DAC 118.
Since the analog input signal 102 is not at baseband, and the sigma-delta converter 112 is operating from a clock source 112 at several times the Nyquist rate, several problems arise. For example, for a sigma-delta converter operating at a five-times oversampling frequency, an analog input signal 102 having a carrier frequency of 200 MHz is sampled at 1 GHz. This is undesirable in that the sigma-delta converter 114 must operate at a high clock rate, which results in a high measure of power dissipation. Additionally, the complexity of designing high-speed digital circuits at rates up to 1 GHz is substantial, and impractical for mass production.
Accordingly, a selective call receiver utilizing a method and apparatus that overcomes the foregoing disadvantages in the prior art is desirable.